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Preliminary Technical Data
FEATURES
High performance 24-bit Sigma-Delta ADC 112dB SNR at 78kHz output data rate 106dB SNR at 312 kHz output data rate 312 kHz maximum fully filtered output word rate Pin-selectable over-sampling rate (64x to 256x) Flexible SPI serial interface Fully differential modulator input On-chip differential amplifier for signal buffering On-chip Reference Buffer Low pass FIR filter Over-range alert pin Digital gain correction registers Power down mode Synchronization of multiple devices via SYNC pin Daisy Chaining
24-Bit, 312 kSPS,109dB ADC, With On-Chip Buffers, Serial Interface AD7764
FUNCTIONAL BLOCK DIAGRAM
VOUTA- VOUTA+ VIN+ VINMCLK AVDD1 DIFF Multi-Bit Sigma-Delta Modulator AVDD2 AVDD3 AVDD3 DVDD Reconstruction OVERRANGE
VINA+ VINAVREF+
+ BUF _
REFGND
AD7764
SYNC RESET/PWRDN Interface Logic and Offset & Gain Correction Registers
Decimation
DEC_RATE
FIR Filter Engine
DECAP RBIAS
SCO
SDI
SDO
FSO
Figure 1.
APPLICATIONS
Data acquisition systems Vibration analysis Instrumentation
PRODUCT OVERVIEW
The AD7764 high performance, 24-bit, sigma delta analog to digital converter combines wide input bandwidth, high speed and performance of 109dB at a 312Khz output data rate with the benefits of sigma delta conversion, while, also offering excellent DC specifications which make the converter ideal for high speed data acquisition of AC signals where DC data is also a requirement. A wide dynamic range combined with significantly reduced anti-aliasing requirements simplifies the design process. The AD7764 offers pin-selectable decimation rates of 64x, 128x, and 256x. Other features include an integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting. The addition of an internal gain register, an over-range alert pin, and a low-pass digital FIR filter make the AD7764 a compact highly integrated data acquisition device requiring minimal peripheral component selection. The AD7764 is ideally suited to applications demanding high SNR without necessitating design of complex front end signal processing.
The differential input is sampled at up to 40MS/s by an analog modulator. The modulator output is processed by a series of low-pass filters. The sample rate, filter corner frequencies and output word rate are determined by the external clock frequency supplied to the AD7764. The reference voltage supplied to the AD7764 determines the analog input range. With a 4V reference, the analog input range is 3.2V differential biased around a common mode of 2V. This common mode biasing can be achieved using the on-chip differential amplifiers, further reducing the external signal conditioning requirements. The AD7764 is available in a 28-lead TSSOP package and is specified over the industrial temperature range from -40C to +85C
RELATED DEVICES
Part no. AD7760 AD7762 AD7763 AD7765 Description 24-bit, 2.5MSPS, 100dB , parallel interface 24-bit, 625ksps, 109dB , parallel interface 24-bit, 625ksps, 109dB , serial interface 24-bit, 156kSPS, 109dB , serial interface
Rev. PrC
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FSI
AD7764 TABLE OF CONTENTS
PRODUCT OVERVIEW............................................................. 1 Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Timing Diagrams.............................................................................. 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Functional Descriptions.......................... 8 Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 12 AD7764 Interface............................................................................ 13 Reading Data............................................................................... 13
Preliminary Technical Data
Writing To The AD7764............................................................ 13 Reading Status and Other Registers......................................... 13 Synchronisation .......................................................................... 13 Daisy Chaining ............................................................................... 14 Clocking the AD7764 .................................................................... 16 Driving The AD7764 ..................................................................... 17 Using The AD7764..................................................................... 18 Bias Resistor Selection ............................................................... 18 AD7764 Registers ........................................................................... 19 Non Bit-Mapped Registers........................................................ 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
Rev. PrC | Page 2 of 21
Preliminary Technical Data SPECIFICATIONS
AD7764
VDD1 = 2.5 V, VDD2 = 5 V, VREF = 4.096 V, TA = +25C, Using the on-chip amplifier with components as shown in Table 7, unless otherwise noted.1 Table 1.
Parameter DYNAMIC PERFORMANCE Decimate by 256 Dynamic Range Signal to Noise Ratio (SNR)2 Spurious Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Test Conditions/Comments MCLK = 40MHz, ODR = 78.125kHz, FIN = 1kHz Sine Wave Modulator inputs shorted Specifcation Unit
Input Amplitude = -0.5dB Input Amplitude = -6dB Input Amplitude = -60dB MCLK = 40MHz, ODR = 156.25kHz, FIN =100kHz Sine Wave Modulator inputs shorted
TBD 115 112 TBD -105 TBD
dB min dB typ dB typ dBFS typ dB typ dB max dB typ dB typ dB min dB typ dB typ dBFS typ dB typ dB max dB typ dB typ dB typ dB min dB typ dBFS typ dB typ dB max dB typ
Decimate by 128 Dynamic Range Signal to Noise Ratio (SNR)2 Spurious Free Dynamic Range (SFDR) Total Harmonic Distortion (THD)
TBD 112 109
Non-harmonic Input Amplitude = -0.5dB Input Amplitude = -6dB Input Amplitude = -6dB, FINA= TBD KHz, FINB=TBD KHz MCLK = 40MHz, ODR = 312.5kHz, FIN = 100kHz Sine Wave Modulator inputs shorted
TBD TBD 109 106
Intermodulation Distortion (IMD) Decimate by 64 Dynamic Range Signal to Noise Ratio (SNR)2 Spurious Free Dynamic Range (SFDR) Total Harmonic Distortion (THD)
Non-harmonic Input Amplitude = -0.5dB Input Amplitude = -6dB Input Amplitude = -6dB, FINA= TBD KHz, FINB=TBD KHz Guaranteed monotonic to 24 bits
TBD TBD
Intermodulation Distortion (IMD) DC ACCURACY Resolution Integral Nonlinearity Zero Error Gain Error Zero Error Drift Gain Error Drift DIGITAL FILTER RESPONSE Decimate by 64 Group Delay Decimate by 128 Group Delay Decimate by 256 Group Delay ANALOG INPUT Differential Input Voltage Input Capacitance
24 0.00076 0.014 0.02 0.018 0.00001 0.0002
Bits LSB typ % typ % max % typ %FS/C typ %FS/C typ
MCLK = 40MHz MCLK = 40MHz MCLK = 40MHz Vin(+) - Vin(-), VREF = 2.5V Vin(+) - Vin(-), VREF = 4.096V At internal buffer inputs
Rev. PrC | Page 3 of 21
89 177 358 2 3.25 5
S typ S typ S typ V pk-pk V pk-pk pF typ
AD7764
Parameter REFERENCE INPUT/OUTPUT VREF Input Voltage VREF Input DC Leakage Current VREF Input Capacitance POWER DISSIPATION Total Power Dissipation POWER REQUIREMENTS AVDD1 (Modulator Supply) AVDD2 (General Supply) AVDD3 (Diff-Amp Supply) AVDD4 (Ref Buffer Supply) DVDD AIDD1 (Modulator) AIDD2 (General) AIDD4 (Reference Buffer) AIDD3 (Diff Amp) DIDD DIGITAL I/O MCLK Input Amplitude3 Input Capacitance Input Leakage Current Three-State Leakage Current (SDO) VINH VINL VOH4 VOL
1 2 3
Preliminary Technical Data
Test Conditions/Comments At modulator inputs VDD3 = 5V 5% Specifcation 55 +4.096 1 5 TBD 5% 5% +2.5 +5 +3.15/+5.25 +3.15/+5.25 +2.5 TBD TBD 10 10 TBD 5 7.3 1 1 TBD TBD 1.5 0.1 Unit pF typ Volts A max pF max mW max Volts Volts V min/max V min/max Volts mA typ mA typ mA typ mA typ mA typ V typ pF typ A/pin max A max V min V max V min V max
5%
AVDD4 = +5V AVDD3 = 5V Clock Stopped
See Terminology section SNR specifications in dBs are referred to a full-scale input, FS. Tested with an input signal at 0.5dB below full scale, unless otherwise specified. While the AD7764 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated. 4 Tested with a 400A load current.
Rev. PrC | Page 4 of 21
Preliminary Technical Data TIMING SPECIFICATIONS
Table 2.AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, TA = +25C, CLOAD = 25pF.
Parameter fMCLK fICLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t121 t13 t14 t15 t16
1
AD7764
Limit at TMIN, TMAX 500 40 250 20 1 x tICLK 1 x tICLK TBD TBD TBD TBD TBD TBD TBD TBD x tSCO TBD TBD TBD TBD TBD TBD
Unit KHz min MHz max kHz min MHz max typ typ typ typ ns max ns min ns max typ typ max min max min min max min
Description Applied Master Clock Frequency Internal Modulator Clock Derived from MCLK. SCO High Period SCO Low Period SCO rising edge to FSO falling edge Data Access time, FSO falling edge to data active Initial Data Access Time, SDO active to SDO valid SDO valid to SCO Rising Edge SCO rising edge to SDO valid SCO rising edge to FSO rising edge FSO rising edge to SDO invalid FSO Low Period FSI Low Period FSI Low Period SCO rising edge to SDI valid SDI valid to SCO rising edge SCO rising edge to SDI valid FSI rising edge to SDI three-state
This is the max time FSI can be held low when writing to an individual (non-daisy chained) AD7764 device.
Rev. PrC | Page 5 of 21
AD7764 TIMING DIAGRAMS
32 x tSCO
Preliminary Technical Data
t1 SCO(O) t2
t10 t3 t8
FSO (O)
t4 t5 t6 t7 t9
SDO(O)
D23
D22
D21
D20
D19
D1
D0
ST4
ST3
ST2
ST1
ST0
0
0
0
Figure 2. Serial Read Timing Diagram
32 x tSCO t1 SCO(O) t2
t12
t11
FSI (I)
t13 t14 t15 RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 RA1 RA0 D15 D14 D1 t16 D0
SDI (I)
Figure 3. AD7764 Register Write
32 x tSCO
SCO (O)
> 8 x tSCO
FSO (O)
SDO (O)
Status Register Contents [31:16]
Don't Care Bits [15:0]
Next Data Read following the Write to Control Register FSI (I)
SDI (I)
Control Register Addr (0x0001)
Control Register Instruction
Figure 4.AD7764 Register read cycle
Rev. PrC | Page 6 of 21
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted Table 3
Parameters AVDD1 to GND (AVDD2, AVDD3, AVDD4) to GND DVDD to GND VINA+ , VINA- to GND1 VIN+ , VIN- to GND1 Digital input voltage to GND2 VREF to GND3 AGND to DGND Input current to any pin except supplies4 Operating temperature range Commercial Storage temperature range Junction temperature TSSOP Package JA thermal impedance JC thermal impedance Lead temperature, soldering Vapor phase (60 secs) Infrared (15 secs) ESD
1
AD7764
Rating -0.3 V to +2.8 V -0.3 V to +6 V -0.3 V to +2.8 V -0.3 V to +6 V -0.3 V to +6 V -0.3 V to +2.8 V -0.3 V to +6 V -0.3 V to +0.3 V TBD -40C to +85C -65C to +150C 150C 143C/W 45C/W 215C 220C TBD kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute maximum voltage for VIN-, VIN+ and VINA-, VINA+ is 6.0V or AVDD3+0.3V, whichever is lower. 2 Absolute maximum voltage on digital inputs is 3.0V or DVDD+ 0.3V, whichever is lower. 3 Absolute maximum voltage on VREF input is 6.0V or AVDD4 + 0.3V, whichever is lower. 4 Transient currents of up to TBD mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrC | Page 7 of 21
AD7764 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
VINA- 1 VOUTA+ 2 VINA+ 3 VOUTA- 4 VIN- 5 VIN+ 6 AVDD2 7 AGND3 8 OVERRANGE 9 SCO 10 FSO 11 SDO 12 SDI 13 FSI 14
28 AVDD3 27 VREF+ 26 REFGND 25 AVDD4
Preliminary Technical Data
AD7764
TOP VIEW (Not to Scale)
24 AVDD1 23 AGND1 22 RBIAS 21 AVDD2 20 AGND2 19 MCLK 18 DEC_RATE 17 DVDD 16 RESET/PWRDWN 15 SYNC
Figure 5. 28-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin Number 24 7, 21 28 25 17 22 23 20 8 26 27 1 2 3 4 5 6 9 10 11 Pin Mnemonic AVDD1 AVDD2 AVDD3 AVDD4 DVDD RBIAS AGND1 AGND2 AGND3 REFGND VREF+ VINAVOUTA+ VINA+ VOUTAVINVIN+ OVERRANGE SCO FSO Description +2.5V power supply to the modulator. This pin should be decoupled to pin TBD with a TBDnF capacitor. +5V power supply. Pin 7 should be decoupled to AGND3(pin 8) with a TBD nF capacitor. Pin 21 should be decoupled to AGND1 (pin 23) with a TBD nF capacitor. +3.3V to +5V power supply for on-board differential ampifier. This pin should be decoupled to AGND1 (pin TBD) with a TBDnF capacitor. +3.3V to +5V power supply for on-board reference buffer. This pin should be decoupled to REFGND (pin TBD) with a TBDnF capacitor. +2.5V power supply for digital circuitry and FIR filter. This pin should be decoupled to the ground plane with a TBDnF capacitor. Bias Current setting pin. A resistor must be inserted between this pin and AGND. For more details on this, see the Bias Resistor Section. Power Supply ground for analog circuitry. Power Supply ground for analog circuitry. Power Supply ground for analog circuitry. Reference Ground. Ground connection for the reference voltage. Reference Input. The input range of this pin is determined by the reference buffer supply voltage (AVDD4). See Reference Section for more details. Negative Input to Differential Amplifier. Positive Output from Differential Amplifier. Positive Input to Differential Amplifier. Negative Output from Differential Amplifier. Negative Input to the Modulator. Positive Input to the Modulator. When this pin outputs a logic high it indicates that the analog input is out of range . This occurs when the magnitude of the differential input is greater than VREF Serial Clock Out. This clock signal is derived from the internal ICLK signal. The frequency of this clock is equal to ICLK. See the AD7764 Interface section for further details. Frame Sync Out. This signal frames the serial data output and is 32 SCO periods wide.
Rev. PrC | Page 8 of 21
Preliminary Technical Data
Pin Number 12 Pin Mnemonic SDO
AD7764
13
SDI
14
FSI
15 16 19 18
SYNC RESET/PWDN MCLK DEC_RATE
Description Serial Data Out. Address, Status and Data bits are clocked out on this line during each serial transfer. Each bit is clocked out on an SCO rising edge and valid on the falling edge. See the AD7764 Interface section for further details. Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event has been latched. 32 bits are required for each write; the first 16-bit word contains the device and register address and the second word contains the data. See the AD7764 Interface section for further details. Frame Sync In. The status of this pin is checked on the falling edge of SCO. If this pin is low then the first data bit is latched in on the next SCO falling edge. See the AD7764 Interface section for further details. Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system. See the AD7764 Interface section for further details. When a logic low is sensed on this pin, the part is powered down and all internal circuitry is reset. Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate will depend on the frequency of this clock. See Clocking the AD7764 Section for more details. This pin selects which of the three decimation modes the AD7764 operates. When logic high is applied to this pin, decimate by 64 mode is selected. Decimate by 128 mode is selected by if the pin is left floating. Decimate by 256 is selected when by applying logic low to the pin.
Rev. PrC | Page 9 of 21
AD7764 TERMINOLOGY
Signal-to-Noise Ratio (SNR) The ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For the AD7763, it is defined as
Preliminary Technical Data
Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Zero Error The zero error is the difference between the ideal midscale input voltage (when both inputs are shorted together) and the actual voltage producing the midscale output code. Zero Error Drift The change in the actual zero error value due to a temperature change of 1C. It is expressed as a percentage of full scale at room temperature. Gain Error The first transition (from 100...000 to 100...001) should occur for an analog voltage 1/2 LSB above the nominal negative full scale. The last transition (from 011...110 to 011...111) should occur for an analog voltage 1 1/2 LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition, from the difference between the ideal levels. Gain Error Drift The change in the actual gain error value due to a temperature change of 1C. It is expressed as a percentage of full scale at room temperature.
THD (dB ) = 20 log where:
V22 + V32 + V42 + V52 + V62 V1
V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Nonharmonic Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, excluding harmonics. Dynamic Range The ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa - fb), while the third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb).
The AD7764 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dB.
Rev. PrC | Page 10 of 21
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
AD7764
Figure 6
Figure 9
Figure 7
Figure 10
Figure 8
Figure 11
Rev. PrC | Page 11 of 21
AD7764 THEORY OF OPERATION
Preliminary Technical Data
BAND OF INTEREST
fICLK/2
BAND OF INTEREST
fICLK/2
BAND OF INTEREST
fICLK/2
Digital filtering has certain advantages over analog filtering. It does not introduce significant noise or distortion and can be made perfectly linear phase. The AD7764 employs three Finite Impulse Response (FIR) filters in series. By using different combinations of decimation ratios, data can be obtained from the AD7764 at three data rates. The first filter receives data from the modulator at ICLK MHz where it is decimated by four to output data at (ICLK/4)
Figure 14 - ADC, Digital Filter Cutoff Frequency
MHz.
The second filter allows the decimation rate to be chosen from 8x to 32x. The third filter has a fixed decimation rate of 2x. Table 5 below shows some characteristics of the digital filtering (See Clocking the AD7764 for details on ICLK).The group delay of the filter is defined to be the delay to the centre of the impulse response and is equal to the computation + filter delays. The delay until valid data is available (the DVALID status bit is set) is equal to 2x the filter delay + the computation delay.
Table 5. Configuration With Default Filter
ICLK Frequency 20 MHz 20 MHz 20 MHz 12.288MHz 12.288MHz 12.288MHz Decimation Rate 64x 128x 256x 64x 128x 256x Data State Fully Filtered Fully Filtered Fully Filtered Fully Filtered Fully Filtered Fully Filtered Computation Delay 2.25S 3.1S 4.65S 3.66S 5.05S 7.57S Filter Delay 87.6S 174S 346.8S 142.6S 283.2S 564.5S Passband Bandwidth 125 kHz 62.5 kHz 31.25 kHz 76.8 kHz 38.4 kHz 19.2 kHz Output Data Rate (ODR) 312.5 kHz 156.25 kHz 78.125 kHz 192 kHz 96 kHz 48 kHz
Rev. PrC | Page 12 of 21
05476-012
The digital filtering which follows the modulator removes the large out-of-band quantization noise (Figure 14) while also reducing the data rate from fICLK at the input of the filter to fICLK/64 or less at the output of the filter, depending on the decimation rate used.
Figure 13. - ADC, Noise Shaping
DIGITAL FILTER CUTOFF FREQUENCY
05476-025
Due to the high over-sampling rate, which spreads the quantization noise from 0 to fICLK, the noise energy contained in the band of interest is reduced (Figure 12). To further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum; so that most of the noise energy is shifted out of the band of interest (Figure 13).
Figure 12. - ADC, Quantization Noise
NOISE SHAPING
05476-024
The AD7764 employs a sigma-delta conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate equal to ICLK.
QUANTIZATION NOISE
Preliminary Technical Data AD7764 INTERFACE
READING DATA
The AD7764 uses an SPI compatible serial interface. The timing diagram in Figure 2 shows how the AD7764 transmits its conversion results. The data being read from the AD7764 is clocked out using the serial clock output, SCO. The SCO frequency is half that of the MCLK input to the AD7764. The conversion result output on the serial data output (SDO) line is framed by the frame synchronization output, FSO, which is sent logic low for 32 SCO cycles. Each bit of the new conversion result is clocked onto the SDO line on the rising SCO edge and is valid on the falling SCO edge. The 32-bit result consists of the 24 data bits which, are followed by 5 status bits followed by a further 3 zeros. The five status bits are :
D7 DVALID OVR LPWR Dec_Rate 1 D3 Dec_Rate 0
AD7764
The next read operation then outputs the contents of the selected register instead of a conversion result. To ensure that the next read cycle contains the contents of the register that has been written to, the write operation to the register in question must be completed a minimum of 8 x tSCO before the falling edge of FSO, which indicates the start of the next read cycle. See Figure 4 for details. Information on the relevant bits that must be set in the control register are provided in the AD7764 Registers section.
SYNCHRONISATION
The SYNC input to the AD7764 provides a synchronization function that allows the user to begin gathering samples of the analog front-end input from a known point in time. The SYNC function allows multiple AD7764s, operated from the same master clock and using the same SYNC signal, to be synchronized so that each ADC simultaneously updates its output register. Using a common SYNC signal to all AD7764 devices in a system allows synchronization to occur. On the falling edge of the SYNC signal the digital filter sequencer is reset to 0. The filter is held in reset state until a rising edge of the SCO senses SYNC high. Thus, to perform a synchronization of devices, a SYNC pulse of a minimum of 2.5 ICLK cycles in length can be applied, synchronous to the falling edge of SCO. On the first rising edge of SCO after SYNC goes logic high, the filter is taken out of reset, and the multiple parts gather input samples synchronously. Following a SYNC, the digital filter needs time to settle before valid data can be read from the AD7764. The user knows there is valid data on the SDO line by checking the DVALID status bit (see D7 in the status bits listing) that is output with each conversion result. The time from the rising edge of SYNC until the DVALID bit is asserted is dependent on the filter configuration used. See the Theory of Operation section and the figures listed in Table 5 for details on calculating the time until DVALID is asserted.
WRITING TO THE AD7764
The AD7764 write operation is shown in Figure 3. The serial writing operation is synchronous to the SCO signal. The status of the frame sync input,FSI , is checked on the falling edge of the SCO signal. If the FSI line is low then the first data bit on the serial data in (SDI) line is latched in on the next SCO falling edge. The active edge of the FSI signal should be set to occur at a position when the SCO signal is high or low, which allows setup and hold time from the SCO falling edge to be met. The width of the FSI signal may be set to between 1 and 32 SCO periods wide. A second or subsequent FSI falling edge which occurs before 32 SCO periods have elapsed will be ignored. Figure 3 details the format for the serial data being written to the AD7764, through the SDI pin. 32 bits are required for a write operation. The first 16 bits are used to select the register address that the data being read is intended for. The second 16 bits contain the data for the selected register. Writing to AD7764 should be allowed at any time even while reading a conversion result. It should be noted that after writing to the devices, valid data will not be output until after the settling time for the filter has elapsed. The DVALID status bit is asserted at this point to indicate that the filter has settled and that valid data is available at the output.
READING STATUS AND OTHER REGISTERS
The AD7764 features a programmable control registers and a read-only status register. To read back the contents of these registers, the user must first write to the control register of the device, setting a bit corresponding to the register to be read.
Rev. PrC | Page 13 of 21
AD7764 DAISY CHAINING
Daisy chaining devices allows numerous devices to use the same digital interface lines. This feature is especially useful for reducing component count and wiring connections, e.g. in isolated multi-converter applications or for systems with a limited interfacing capacity. Data read-back is analogous to clocking a shift register. The block diagram in Figure 15 shows the way in which devices must be connected in order to achieve daisy chain functionality. Figure 15 shows four AD7764 devices daisy chained together with a common MCLK signal applied, this can only work in decimate by 128 or 256 modes.
Preliminary Technical Data
conversion result is output from the device labeled AD7764(A). This 32-bit conversion result is then followed by the conversion results from the devices B,C and D respectively with all conversion results output in an MSB first sequence. The signals output from the daisy chain are the stream of conversion results from the SDO pin of AD7764(A) and the FSO signal also output by the first device in the chain (AD7764(A)). The falling edge of FSO signals the MSB of the first conversion output in the chain. FSO stays logic low throughout the 32 SCO clock periods needed to output the AD7764(A) result and thereafter goes logic high during the output of the conversion results from the devices B,C, and D. The maximum number of devices that can be daisy chained is dependent on the decimation rate the user selects. The max number of devices that can be daisy chained can be calculated simply by dividing the chosen decimation rate by 32(the number of bits that must be clocked out for each conversion). Table 6 shows give the maximum number of chained devices for each decimation rate.
Table 6 Maximum length of device chain for all decimation rates
Decimation Rate x256 x128 x64 Maximum length of chain 8 4 2
Reading Data in Daisychain Mode
The SDO line of AD7764 (A) provides the output data from the chain of AD7764 converters. The last device in the chain (AD7764(D) in Figure 15) will have its Serial Data In (SDI) pin connected to ground. All the devices in the chain must use common MCLK and SYNC signals. To enable the daisy chain conversion process, apply a common SYNC pulse to all devices (see synchronization of devices). After applying a SYNC pulse to all the devices there is a delay of TBD SCO periods before valid conversion data appears at the output of the chain of devices. As shown in Figure 16 the first
FSI
FSI SDI SDI SYNC
AD7764 (D) SDO
FSI SDI SYNC
AD7764 (C) SDO
FSI SDI SYNC
AD7764 (B) SDO
FSI SDI SYNC
AD7764 (A)
FSO SDO
MCLK SYNC
MCLK
MCLK
MCLK
MCLK
Figure 15. Daisy Chaining 4xAD7764 devices in decimate by 128 mode using a 40Mhz MCLK signal.
32 x tSCO SCO SDO (A) FSO (A) SDI (A) = SDO (B) SDI (B) = SDO (C) SDI (C) = SDO (D) AD7764 (B) AD7764 (C) AD7764 (D) AD7764 (A) 32-Bit O/P
32 x tSCO
32 x tSCO
32 x tSCO
AD7764 (B) 32-Bit O/P
AD7764 (C) 32-Bit O/P
AD7764 (D) 32-Bit O/P
AD7764 (A) 32-Bit O/P
AD7764 (B) 32-Bit O/P
AD7764 (C) AD7764 (D)
AD7764 (D)
AD7764 (B) AD7764 (C) AD7764 (D)
AD7764 (C) AD7764 (D)
Figure 16. Daisychain mode, Data read timing diagram (for daisychain configuration shown in Figure 15).
Rev. PrC | Page 14 of 21
Preliminary Technical Data
Writing Data in Daisychain Mode
Writing to AD7764 devices in daisy chain mode is similar to writing to a single device. The serial writing operation is synchronous to the SCO signal. The status of the frame sync input,FSI , is checked on the falling edge of the SCO signal. If the FSI line is low then the first data bit on the serial data in (SDI) line is latched in on the next SCO falling edge. Writing data to the AD7764 in Daisy Chain mode operates with the same timing structure as per writing to a single device as shown in Figure 3. The difference between writing to a single device and a number of daisychained devices is in the implementation of the FSI signal. The number of devices that are in the daisy chain determines the period for which the FSI signal must remain logic low. If the user wishes to write to n number of devices in the daisy chain, the period between the falling edge of FSI and the rising edge of FSI must be be
AD7764
between 32 x (n-1) to 32 x n, SCLK periods. For example, if three AD7764 devices are being written to in Daisychain mode FSI is logic low for between 32 x(3-1) to 32 x 3 SCLK pulses. i.e. the rising edge of FSI must occur between the 64th and 96th SCO period. The AD7764 devices may be written to at any time. The falling edge of FSI overrides all attempts to read data from the SDO pin. In the case of a daisy chain the FSI signal remaining logic low for more than 32 SCO periods will indicate to the AD7764 device that there are more devices further on in the chain. This means the AD7764 in question will direct data that is input on the SDI pin to its SDO pin. This ensures that data is passed to the next device in the chain. Synchronise all the AD7764 devices in the chain after the write is completed.
FSI
FSI SDI SDI SYNC
AD7764 (D) SDO
FSI SDI SYNC
AD7764 (C) SDO
FSI SDI SYNC
AD7764 (B) SDO
FSI SDI SYNC
AD7764 (A)
FSO SDO
MCLK SYNC
MCLK
MCLK
MCLK
MCLK
Figure 17.Writing to AD7764 Daisy chain configuration
Rev. PrC | Page 15 of 21
AD7764 CLOCKING THE AD7764
The AD7764 requires an external low jitter clock source. This signal is applied to the MCLK pin. An internal clock signal (ICLK) is derived from the MCLK input signal. This ICLK controls all the internal operation of the AD7764. The maximum ICLK frequency is 20MHz. The ICLK is generated as follows: ICLK = MCLK/2 If the user wishes to get output data rates equal to those used in audio systems, a 12.288 MHz ICLK frequency can be used. As shown in Table 5, output data rates of 192, 96kHz and 48kHz are achievable with this ICLK frequency. The MCLK jitter requirements depend on a number of factors and are given by the following equation:
Preliminary Technical Data
EXAMPLE 2
Taking a second example from Table 5, where: ODR = 48kHz fICLK = 12.288MHz fIN (max) = 19.2kHz SNR = 112dB
t j ( RMS ) =
256 = 333 ps 2 x x 19.2 x 10 3 x 105.75
t j ( RMS ) =
Where:
OSR 2 x x f IN x 10
SNR ( dB ) 20
The input amplitude also has an effect on these jitter figures. If, for example, the input level was 3dB down from full-scale , the allowable jitter would be increased by a factor of 2 increasing the figure calculated in the first example from 40.84ps to 57.75ps RMS. This is because the maximum slew rate is reduced by a reduction in amplitude. Figure 18 and Figure 19 illustrate this point showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes.
OSR = Over-sampling ratio = f ICLK
ODR
fIN = Maximum Input Frequency
SNR(dB) = Target SNR.
EXAMPLE 1
This example can be taken from Table 5, where:
ODR = 312.5 kHz fICLK = 20MHz fIN (max) = 156.25 kHz SNR = 106dB
Figure 18. Maximum Slew Rate of Sine Wave with Amplitude of 2V Pk-Pk
t j ( RMS ) =
64 = 40.84 ps 2 x x 156.25 x 103 x 105.3
This is the maximum allowable clock jitter for a full-scale 156.25kHz input tone with the given ICLK and Output Data Rate.
Figure 19. Maximum Slew Rate of Same Frequency Sine Wave with Amplitude of 1V Pk-Pk
Rev. PrC | Page 16 of 21
Preliminary Technical Data DRIVING THE AD7764
The AD7764 has an on-chip differential amplifier. This amplifier will operate with a supply voltage (AVDD3) from 3V to 5.5V. For a 4.096V reference, the supply voltage must be 5V. To achieve the specified performance in normal power mode, the differential amplifier should be configured as a first order anti-alias filter as shown in Figure 20. Any additional filtering should be carried out in previous stages using low noise, highperformance op-amps such as the AD8021. Suitable component values for the first order filter are listed in Table 7. Using the first row as an example would yield a 10dB attenuation at the first alias point of 19MHz.
CFB
+2.5V +3.685V 0V A -2.5V +0.410V +2.048V
AD7764
VIN+
+2.5V B 0V
+3.685V
+2.048V
VIN-
-2.5V
+0.410V
Figure 21. Differential Amplifier Signal Conditioning.
CFB
RFB
2R
A
RIN CS A1
RM VIN- RM VIN+ RFB CFB
05476-016
VIN
2R AD8021 R
RIN CS
RFB
VINA1 VIN+
B RIN
RIN
RFB
CFB
Figure 20. Differential Amplifier Configuration
Figure 22. Single Ended to Differential Conversion
Table 7.First-Order Filter Component Values
VREF 4.096v RIN 4.75k RFB 3.01k RM 43 CS 1.2pF CFB 33pF
Figure 21 shows the signal conditioning that occurs using the circuit in Figure 20 with a 2.5V input signal biased around ground using the component values and conditions in Table 7. The differential amplifier will always bias the output signal to sit on the optimum common mode of VREF/2, in this case 2.048V. The signal is also scaled to give the maximum allowable voltage swing with this reference value. This is calculated as 80% of VREF, i.e. 0.8 x 4.096V 3.275V peak to peak on each input. To obtain maximum performance from the AD7764, it is advisable to drive the ADC with differential signals. Figure 22 shows how a bipolar, single-ended signal biased around ground can drive the AD7764 with the use of an external op amp, such as the AD8021 With a 4.096 V reference, a 5 V supply must be provided to the reference buffer (AVDD4).
The AD7764 employs a double sampling front end,as shown in Figure Figure 23. For simplicity, only the equivalent input circuitry for VIN+ is shown. The equivalent circuitry for VIN- is the same.
VIN+ CPA SH1 CPB1 SS3 ANALOG MODULATOR SS1 CS1 SH3
SS2
CS2 SH4
05477-043
SH2
CPB2
SS4
Figure 23. Equivalent Input Circuit
Rev. PrC | Page 17 of 21
05476-017
AD7764
The sampling switches SS1 and SS3 are driven by ICLK, whereas, the sampling switches SS2 and SS4 are driven by ICLK. When ICLK is high, the analog input voltage is connected to CS1. on the falling edge of ICLK , the SS1 and SS3 switches open and the analog input is sampled on CS1. Similarly, when ICLK is low, the analog input voltage is connected to CS2. On the rising edge of ICLK, the SS2 and SS4 switches open, and the analog input is sampled on CS2. Capacitors CPA, CPB1 and CPB2 represent parasitic capacitances which include the junction capacitances associated with the MOS switches.
Table 8 Equivalent Component Values
CS1 13pF CS2 13pF CPA 13pF CPB1/2 5pF
Preliminary Technical Data
BIAS RESISTOR SELECTION
The AD7764 requires a resistor to be connected between the RBIAS pin and AGND. The value for this resistor is dependant on the reference voltage being applied to the device. The resistor value should be selected to give a current of 25A through the resistor to ground. For a 4.096V reference voltage, the correct resistor value is 160k.
USING THE AD7764
The following is the recommended sequence for powering up and using the AD7764. 1. 2. 3. 4. 5. Apply Power Start clock oscillator, applying MCLK Take RESET low for a minimum of 1 MCLK cycle Wait a minimum of 2 MCLK cycles after RESET has been released. In circumstances where multiple parts are being synchronized, a SYNC pulse must be applied to the parts, otherwise no SYNC pulse is required.
Conditions for applying the SYNC pulse: (a) The issue of a SYNC pulse to the part must not coincide with a write to the part. (b) Ensure that the SYNC pulse is taken low for a minimum of 2.5 ICLK cycles. Data can now be read from the part using the default gain and over range threshold values. The conversion data read will not be valid however until the settling time of the filter has passed. When this has occurred, the DVALID status bit read will be set indicating that the data is indeed valid. Values for gain and over range threshold registers can be written or read at this stage.
Rev. PrC | Page 18 of 21
Preliminary Technical Data AD7764 REGISTERS
AD7764
The AD7764 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and differential amplifier. and also provides the user the option to power down the AD7764. There are also digital gain and over-range threshold registers. Writing to these registers involves writing the register address first, then a 16-bit data word. Register Addresses, details of individual bits and default values are given here:
Table 9 Control Register (Address 0x0001, Default Value 0x001A)
MSB 0 RD Ovr RD Gain 0 RD Stat 0 SYNC 0 Bypass Ref 0 0 0 Pwr Down 0 Ref Buf Off LSB Amp Off
Bit 14 13 11 9 7 3 2 1 0
Mnemonic RD Ovr8,9 RD Gain8,9 RD Stat8,9 SYNC8 By-Pass Ref Pwr Down 0 Ref Buf Off Amp Off
Comment Read Overrange. If this bit has been set, the next read operation will output the contents of the Overrange Threshold Register instead of a conversion result. Read Gain. If this bit has been set, the next read operation will output the contents of the digital Gain Register. Read Status. If this bit has been set, the next read operation will output the contents of the Status Register. Synchronize. Setting this bit will initiate in internal synchronisation routine. Setting this bit simultaneously on multiple devices will synchronize all filters. By-passes reference buffer if the buffer is off. A logic high powers the part down, however, no reset is done. Writing a 0 to this bit powers the part back up. Set this bit to logic zero. Asserting this bit powers down the reference buffer. Asserting this bit switches the differential amplifier off.
Table 10. Status Register (Read Only)
MSB PART 1 1 DIE 2 DIE 1 DIE 0 DVALID LPWR OVR 0 1 0 Ref Buf On Amp On 0 DEC 1 LSB DEC 0
Bit 15,14 13 to 11 10 9 8 4 3 1 to 0
8 9
Mnemonic PART1:0 DIE2:0 DVALID 0 OVR Ref Buf On Amp On DEC1:0
Comment Part Number. These bits will be constant for the AD7764. Die Number. These bits will reflect the current AD7764 die number for identification purposes within a system. Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation. This bit is set to logic zero. If the current analog input exceeds the current overrange threshold, this bit will be set. This bit is set when the reference buffer is in use. This bit is set when the input amplifier is in use. Decimation Rate. These bits correspond to decimation rate that is in use.
Bits 14 to 11 & bit 9 are self clearing bits. Only one of the bits may be set in any write operation as they all determine the contents of the next operation.
Rev. PrC | Page 19 of 21
AD7764
NON BIT-MAPPED REGISTERS
Gain Register (Address 0x0004, Default Value 0xA000)
Preliminary Technical Data
The Gain Register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a full scale digital output when the input is at 80% of VREF. This ties in with the maximum analog input range of 80% of VREF Pk-Pk.
Over Range Register (Address 0x0005, Default Value 0xCCCC)
The Over Range register value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of VREF (the maximum permitted analog input voltage) Assuming VREF = 4.096V, the bit will then be set when the input voltage exceeds approximately 6.55v pk-pk differential. Note that the over-range bit is also set immediately if the analog input voltage exceeds 100% of VREF for more than 4 consecutive samples at the modulator rate.
Rev. PrC | Page 20 of 21
Preliminary Technical Data OUTLINE DIMENSIONS
AD7764
Figure 24. 28-Lead Thin Shrink Small Outline [TSSOP] (RU-28)--Dimensions shown in millimeters
ORDERING GUIDE
Model AD7764BRUZ Temperature Range -40C to +85C Package Description Thin Shrink Small Outline Package Option RU-28
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. PR06518-0-11/06(PrC)
Rev. PrC | Page 21 of 21

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